Integrated circuit fabrication often includes forming an isolation region to define one or more active regions in a substrate of a semiconductor structure. One way to define an isolation region is to form one or more trenches in the substrate using one or more etching processes while masking a silicon or other substrate over what is to be the active region. As an example, this process may be referred to as shallow trench isolation (STI). Subsequent to formation, the trenches may be filled with a fill oxide. The etching processes for forming the isolation regions may lead to various problems, including fill oxide erosion at the interface between the fill oxide and the substrate (i.e. a depression formed at the interface). These problems may degrade transistor performance. For example, these problems may lead to an undesirable “double-hump” in the current-voltage (I-V) curve for the transistor.
Current techniques for reducing fill oxide erosion during formation of the trenches include a “pullback” process performed on a nitride or other mask layer (which overlies the silicon to define the active region). Such pullback processes include a wet chemistry used after etching the trench and either before or after lining the trench with a desired liner oxide layer. However, current pullback processes are problematic. For example, the mask layer may be oxidized by the process for forming the liner oxide layer, creating a variable-depth silicon oxy-nitride layer. This may cause significant variation in the subsequent wet etch rate for stripping the mask layer. As another example, a hydrofluoric (HF) process used to deglaze the oxy-nitride layer prior to hot phosphoric acid being used during nitride removal may erode the liner oxide layer.